1. Field of the Invention
This invention relates to semiconductor memory devices and, in particular, to dynamic random access memory devices (DRAMs) having a wide bandwidth, fast read and write access and programmable number of data read and data write lines.
2. Description of the Related Art
DRAMs contain an array of individual memory cells. Typically, each DRAM memory cell comprises a capacitor for holding a charge and an access transistor for accessing the capacitor charge. The charge is representative of a data bit and can be either high voltage or low voltage (representing, e.g., a logical "1" or a logical "0," respectively). Data can be stored in memory during write operations or read from memory during read operations.
Refresh, read, and write operations in present-day DRAMs are typically performed for all cells in one row simultaneously. Data is read from memory by activating a row, referred to as a word line, which couples all memory cells corresponding to that row to digit or bit lines which define the columns of the array. When a particular word line and bit line are activated, a sense amplifier detects and amplifies the data in the addressed cell by measuring the potential difference on the activated bit line corresponding to the content of the memory cell connected to the activated word line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc. and incorporated by reference herein.
An embedded DRAM resides on a complex semiconductor circuit containing significant amounts of both DRAM and logic units (for example, a processor). This results in a compact design with minimal propagation distances between the logic units and the memory cells. Embedded DRAM also offers the advantages of simpler system-level design, fewer packages with fewer pins, reduced part count, and lower power consumption. This reduction in external circuit connections increases the efficiency of the DRAM and the overall logic processing device or application. For example, the bandwidth, the number of input and output pins, of the DRAM can increase because less circuitry is required to operate the DRAM. Speed also increases since the logic and control signals, as well as the input and output data, travel shorter distances.
FIG. 1 illustrates one example of a semiconductor circuit 50 having a processor 52 and embedded DRAM 54. Although a processor 52 is illustrated in FIG. 1, the circuit 50 could also utilize a co-processor or other logical device. Likewise, the circuit 50 could utilize synchronous graphic random access memory (SGRAM) instead of embedded DRAM 54. SGRAM is specifically designed for video applications but generally operates in a similar manner as the conventional embedded DRAM 54.
FIG. 2 illustrates a portion of the architecture of a conventional embedded DRAM 54. The DRAM 54 includes several arrays of memory cells 60, data path circuits 56, sense amplifier circuits 64 and row decoder circuits 66a, 66b, 66c (collectively referred to as row decoders 66). The row decoder circuits 66 are used to activate rows of memory within the arrays 60 based upon an address supplied by control logic. The middle row decoder 66b is used to activate rows in the two arrays 60 adjacent to it while the two outside row decoders 66a, 66c are used to activate rows in the single array 60 that they are adjacent to. Column select signals, also provided by control logic, are used to activate specified columns of memory within the arrays 60. The data path circuits 56 and the arrays 60 are connected (through the sense amplifier circuits 64) by numerous IO lines 62 (although only a small number of IO lines are illustrated in FIG. 2). Accordingly, data travels along the IO lines 62 between the arrays 60 and data path circuits 56.
A conventional data path circuit 56 generally includes read and write drivers and data read and data write lines. Data read lines allow the data path circuits 56 to output data read from the arrays 60 to a logical unit (e.g., the processor in FIG. 1). Data write lines allow the data path circuit 56 to input data from a logical unit and to write the data into the arrays 60. Data read and data write Lines are sometimes referred to as I/O lines, since they are usually connected to input/output pins or buffers, which are not to be confused with the IO lines 64 providing a path between the sense amplifier circuits 56 and the memory arrays 60.
Although the conventional embedded DRAM has performed well in the past, the evolution of current technology requires faster memory with larger bandwidths. The architecture illustrated in FIG. 2 utilizes very long IO lines 62 which leads to slower speeds because a longer time is required to access the individual memory cells of the array 60, particularly for memory cells located the farthest away from the data path circuits 56 because only one row at a time can be addressed for all the IO lines 62. In addition, the bandwidth of the DRAM 54 is also restricted by the use of the numerous long IO lines 62. Therefore, to accommodate today's technology, there is still a desire and need to increase the bandwidth of embedded DRAM circuits while also increasing the speed of these circuits.
Memory tests on embedded DRAM circuits are typically performed by the manufacturer during production and fabrication and also by a downstream manufacturer of a computer or processor controlled system as well as by an end-user during computer initialization to determine if the circuits are operating as intended. One conventional method of testing memory is to utilize address compression. Briefly, address compression is accomplished by treating certain addresses as "don't care" address locations. These locations correspond to specific input or output pins and are compared together with a special compare circuit. The compare circuit determines if the data from each address location is the same. If they are not the same, at least one of the address locations is defective.
Addressed compression greatly increases the speeds of the DRAM test. Unfortunately, address compression can not be fully utilized in conventional embedded DRAMs because the FIG. 2 architecture of the conventional embedded DRAM prevents the activation of more than one row of memory cells at a time per set of IO lines 62. Therefore, there is a need to enhance the testing of embedded DRAM circuits.
Since embedded DRAM circuits are usually tailored for the application or process desired, there exists a need to easily add the desired amount of data read and data write lines (I/O lines corresponding to output and input buffers and pins) for an application without a major reconfiguration of the memory circuit architecture (this addition of a number of I/O lines as desired is referred to as programmable data read and data write lines or programmable I/O's).